Computer Organization and Embedded System
NEC Computer Engineering · 1,518 practice MCQs
The chapter on Computer Organization and Embedded Systems is essential for understanding the architecture and functioning of computer systems, particularly in the context of embedded applications. This chapter covers critical topics such as instruction pipelining, memory management, and system architecture, which are vital for the NEC licensing exam.
To excel in this chapter, focus on practicing the 1518 multiple-choice questions (MCQs) provided. These questions are designed to test your knowledge and application of concepts relevant to the exam, ensuring you are well-prepared for the challenges ahead.
Sample questions with answers
1.An ASIP designed for artificial intelligence tasks would feature:
- A.Disk scheduling features
- B.Instructions for matrix multiplication
- C.Highly associative caches
- D.Shaders for graphics processing
Why: Instructions for matrix multiplication are essential for artificial intelligence tasks as they often involve heavy computations with matrices, making this the correct choice.
2.What is the primary role of a reorder buffer in out-of-order processors?
- A.Enabling SIMD operations
- B.Minimizing cache misses
- C.Increasing instruction set size
- D.Ensuring precise exceptions and in-order commits
Why: The reorder buffer's primary function is to ensure that instructions are committed in the order they were issued, which is crucial for maintaining precise exceptions in out-of-order processors.
3.What is the main factor affecting hit time?
- A.Replacement approach
- B.Size of blocks
- C.Degree of associativity
- D.Total cache size
Why: The total cache size directly affects hit time because a larger cache can store more data, reducing the likelihood of cache misses and improving access speed.
4.What is the bisection bandwidth for a 2D mesh consisting of N nodes?
- A.log₂N
- B.1
- C.√N
- D.N/2
Why: The bisection bandwidth for a 2D mesh network is √N because this configuration allows for a maximum of √N connections to be made across the network, optimizing data transfer.
5.Scratchpad memory is favored over cache in embedded systems when:
- A.Deterministic response time is needed
- B.Power usage is not a concern
- C.Compiler flexibility is key
- D.Dynamic memory management is required
Why: Scratchpad memory is preferred in embedded systems when deterministic response time is crucial, as it provides predictable access times unlike caches which can introduce variability.
6.In UNIX-like operating systems, how are device drivers typically implemented?
- A.As kernel modules
- B.Only as assembly routines
- C.In shared libraries
- D.As user-space daemons
Why: Device drivers in UNIX-like operating systems are typically implemented as kernel modules to allow them direct access to hardware and efficient communication with the kernel.
7.Why do variable-length instructions create issues in instruction pipelining?
- A.They need multiple opcodes for each instruction
- B.They can't incorporate immediate operands
- C.Execution durations differ significantly
- D.The fetch stage struggles to determine instruction boundaries
Why: Variable-length instructions complicate instruction pipelining because the fetch stage has difficulty determining where one instruction ends and the next begins, leading to potential pipeline stalls.
8.NUMA multiprocessors need to handle:
- A.Single bus arbitration
- B.Cache bypass
- C.Non-uniform memory access latency
- D.Instruction stalls
Why: NUMA multiprocessors must manage non-uniform memory access latency, as memory access times can vary significantly depending on the processor's location relative to the memory.
9.What is the abstraction boundary from the perspective of an embedded programmer?
- A.Pipeline management
- B.Transistor arrangement
- C.Instruction Set Architecture level
- D.Gate-level design
Why: For an embedded programmer, the abstraction boundary is at the Instruction Set Architecture level, where they interact with the hardware through a defined set of instructions.
10.What do custom single-purpose processors achieve?
- A.Always the lowest latency for interrupts
- B.Unlimited adaptability
- C.Maximum programmability
- D.Optimal efficiency for specific tasks
Why: Custom single-purpose processors are designed for optimal efficiency for specific tasks, allowing them to execute those tasks faster and with less power compared to general-purpose processors.
11.Which type in VHDL is only for decimal simulations and cannot be synthesized?
- A.SIGNED
- B.STD_LOGIC_VECTOR
- C.REAL
- D.UNSIGNED
Why: The REAL type in VHDL is used for decimal simulations and cannot be synthesized into hardware, making it unsuitable for actual implementation in digital circuits.
12.In the context of CPU architecture, what does the term 'datapath' mean?
- A.Parts that transfer and handle data
- B.Just the ALU
- C.Cache memory only
- D.Only the control unit
Why: In CPU architecture, the term 'datapath' refers to the components that transfer and handle data, including registers, multiplexers, and the ALU, which work together to execute instructions.
Practice all 1,518 Computer Organization and Embedded System questions
Adaptive mock tests, AI explanations on every question, and a personalized study plan.
Frequently asked questions
- What is the focus of the Computer Organization and Embedded System chapter?
- The chapter focuses on computer architecture, memory management, and embedded system design, crucial for NEC exam success.
- How many practice MCQs are available for this chapter?
- There are 1518 practice MCQs available for this chapter.
- Why are variable-length instructions problematic in pipelining?
- Variable-length instructions can lead to complexity in instruction fetching and decoding, causing pipeline stalls.
- What is the role of a reorder buffer in out-of-order processors?
- The reorder buffer helps maintain the correct order of instruction execution and ensures that results are committed in the proper sequence.
- When is scratchpad memory preferred over cache in embedded systems?
- Scratchpad memory is favored when deterministic performance and lower latency are required, as it avoids the unpredictability of cache.